Manufacturing non-uniform surface channel type MOS transistors has less effect on the characteristics of the transistors than manufacturing non-uniform buried channel type MOS transistors. As a result, reducing a threshold voltage and heightening the driving capability in the surface channel type MOS transistor is easier, and thus, the surface channel type MOS transistor is better suited for developing smaller and faster LSI circuits. In order to form surface channel type CMOS transistors, an NMOS transistor and a PMOS transistor are formed. Also, an N.sup.+ type silicon film is used as the gate electrode of the NMOS transistor, and a P.sup.+ type silicon film is used as the gate electrode of the PMOS transistor. In order to understand the benefits of the present invention, two conventional devices will be described.
FIG. 5 shows the cross-sectional structure of a conventional CMOS transistor formed on a N type silicon substrate 2. Specifically, a P type well 3 formed in an N type silicon substrate 2, and an NMOS transistor is formed on the P type well 3. Also, the gate electrode 10 of the NMOS transistor is made of N.sup.+ polycrystalline silicon. Also, a PMOS transistor is formed on the N type silicon substrate 2, and the gate electrode 12 of the PMOS transistor is made of P.sup.+ polycrystalline silicon.
The method for manufacturing the device shown in FIG. 5 is illustrated in FIGS. 6(a) to 6(c). As shown in FIG. 6(a), the N type silicon substrate 2 is provided, and a P type well 3 is formed in the substrate 2 by a well-known method. Then, a device isolation oxide film 5 and a gate oxide film 6 are formed over the substrate 2 and P type well 3. Afterwards, a polycrystalline silicon film 7 is grown entirely over the oxide films 5 and 6, and a metal film 25 (e.g. Ti) is grown entirely over the silicon film 7. Then, a patterned photoresist 26 is placed over the metal film 25, and portions of the metal film 25 and the polycrystalline silicon film 7 are removed via photolithography and etching techniques by using the photoresist 26 as a mask.
As shown in FIG. 6(b), the photoresist 26 is removed, a photoresist 27 is formed over the PMOS transistor region of the device. Then, arsenic ions As.sup.+ are implanted into the P type well 3 and the polycrystalline silicon film 7 in the NMOS transistor region. When the ions As.sup.+ are implanted, impurities pierce through the metal film 25 and are implanted into the polycrystalline silicon film 7. As a result, film 7 is transformed into an N.sup.+ polycrystalline silicon film to form the gate electrode 10 of the NMOS transistor. Also, the implanted ions As.sup.+ form a source/drain region 9 in the P type well 3.
As shown in FIG. 6(c), the photoresist 27 is removed, and a photoresist 28 is formed over the NMOS transistor region. Afterwards, boron ions B.sup.+ are implanted into the substrate 2 and polycrystalline silicon film 7 in the PMOS transistor region. When the ions B.sup.+ are implanted, impurities pierce through the metal film 25 and are implanted into the polycrystalline silicon film 7. Thus, the film 7 is transformed into a P.sup.+ polycrystalline silicon film to form the gate electrode 12 of the PMOS transistor. Also, the ions B.sup.+ implanted in the substrate 2 form a source/drain region 11.
Subsequently, a heat treatment is conducted to activate the impurities in the source/drain regions 9 and 11 and the gate electrodes 10 and 12. As a result, the manufacture of the device shown in FIG. 5 is completed.
Normally, in order to improve the performance of the transistors, a depletion layer must be prevented from being formed in the gate electrodes 10 and 12 when a bias is applied to the gate electrodes 10 and 12. In order to prevent the formation of the depletion layer, high concentrations of impurities must be implanted in the region of the gate electrode 10 which comes in contact with the gate oxide film 6, and a heat treatment must be conducted after the ion implantation. In the conventional manufacturing method discussed above, impurities (i.e. the arsenic ions As.sup.+ or boron ions B.sup.+) are implanted into the films 6 and 7 to form the source/drain region 9 (or 11) of the NMOS (or PMOS) transistor and are simultaneously added to the polycrystalline silicon film 7 to form the gate electrode 10 (or 12).
The boron ions B.sup.+ used to form the source/drain region 11 of the PMOS transistor have a low mass number, and thus boron is easily implanted deep into silicon. As a result, if the boron ions B.sup.+ implanted into the polycrystalline silicon film 7 are introduced into the gate oxide film 6 during the ion implantation and the subsequent heat treatment, the reliability of the gate oxide film 6 dramatically decreases. Thus, the characteristics of the transistor become extremely non-uniform due to the manufacturing non-uniformity.
Meanwhile, arsenic ions As.sup.+ have a high mass number and therefore, are used to form a shallow junction when the source/drain region 9 of the NMOS transistor has a gate length on the order of less than a micron. Accordingly, if the polycrystalline silicon film 7 is relatively thick, a sufficient amount of arsenic ions As.sup.+ does not reach the region of the gate electrode 10 which comes into contact with the gate oxide film 6 below the polycrystalline silicon film 7. As a result, the gate electrode 10 is depleted of impurities, and the driving capability of the NMOS transistor is lowered.
In the above manufacturing method, the polycrystalline silicon film 7 used for the NMOS transistor and the polycrystalline silicon film 7 used for the PMOS transistor have the same thickness. Therefore, thickness of the polycrystalline silicon film 7 for both the NMOS transistor and the PMOS transistor must be optimized to account for the above effects that the thickness of the film 7 has on both the NMOS and PMOS transistors. However, if the acceleration voltage of ion implantation is adjusted based on thicknesses of the gate electrodes in order to prevent the boron ions B.sup.+ from becoming implanted too deeply in the PMOS transistor and to prevent the gate electrode 10 in the NMOS transistor from being depleted, the depths and concentrations of the impurities in the source/drain regions 9 and 11 of the transistors varies and severely and adversely influences the characteristics of the NMOS transistor and the PMOS transistor. Thus, if the gate electrode 10 (or 12) and the source/drain region 9 (or 11) are formed simultaneously, optimizing the characteristics of the gate electrodes 10 and 12 for both the NMOS transistor and the PMOS transistor is difficult.
The above description refers to an example of a MOS transistor having a polyside gate structure in which a gate electrode is processed after the polycrystalline silicon film 7 and the metal film 25 are formed. The same problem also occurs in a MOS transistor having a saliside structure in which only a polycrystalline silicon film is used as a gate electrode until a source/drain region is formed, and then, the surfaces of the gate electrode and the source/drain region are formed into metal silicide.
A method for manufacturing CMOS transistors which attempts to avoid the above problems is disclosed in Japanese Unexamined Patent Publication No. 62-281462. In particular, ions are not implanted into a polycrystalline silicon film 7 to form the gate electrode 10 (or 12) when ions are implanted to form the source/drain region 9 (or 11). A description of the method will be described below in conjunction with FIGS. 7(a) to 7(c) and FIGS. 8(a) to 8(b).
As shown in FIG. 7(a), an N type silicon substrate 2 is provided, and a P type well 3 is formed on the substrate 2, Then, a device isolation oxide film 5 and a gate oxide film 6 are formed on the substrate 2 and the well 3, and a polycrystalline silicon film 7 is grown on the entire surface. Afterwards, a patterned photoresist 29 is formed over the polycrystalline silicon film 7, and phosphorous and arsenic ions P.sup.+ and As.sup.+ are implanted into a region of the film 7 which is slightly wider than the gate electrode of the NMOS transistor to transform the region into an N.sup.+ type region 10.
As shown in FIG. 7(b), the photoresist 29 is removed, and a patterned photoresist 30 is formed over the polycrystalline silicon film 7. Then, boron ions B.sup.+ are implanted into a region of the film which is slightly wider than the gate electrode of the PMOS transistor to transform the region into a P.sup.+ type region 12.
As shown in FIG. 7(c), the photoresist 30 is removed, and a metal film 25 is formed over the entire surface of the polycrystalline silicon film 7. Then, a patterned photoresist 26 is formed over the metal film 25 and the polycrystalline silicon film 7, and portions of the films 25 and 7 are removed via photolithography and etching techniques by using the photoresist 26 as a mask. Thus, the gate electrode 10 having an N.sup.+ polycrystalline silicon film is formed, and the gate electrode 12 having a P.sup.+ polycrystalline silicon film is formed. The photoresist 26 is formed such that it has a slightly smaller width than the regions 10 and 12 of the film 7 into which the impurities are implanted.
As shown in FIG. 8(a), the photoresist 26 is removed, and a photoresist 27 is formed over the PMOS transistor region. Then, phosphorous ions P.sup.+ and arsenic ions As.sup.+ are implanted into the P type well 3 to form the source/drain region 9 of the NMOS transistor. At this time, ions P.sup.+ and As.sup.+ are also implanted into the gate electrode 10.
As shown in FIG. 8(b), the photoresist 27 is removed, and a photoresist 28 is formed over the NMOS transistor region. Then, boron ions B.sup.+ are implanted into the substrate 2 to form the source/drain region 11 of the PMOS transistor. At this time, ions B.sup.+ are also implanted into the gate electrode 12. Afterwards, a heat treatment is conducted to activate the impurities in the source/drain regions 9 and 11.
In the conventional device and method shown in FIGS. 5 and 6, ions are implanted into the source/drain region of a transistor and are simultaneously implanted into the gate electrode of the transistor. As a result, obtaining desired transistor characteristics while preventing the deterioration of the performance of the gate electrode has been difficult.
Also, in the conventional method shown in FIGS. 7 and 8, the ions are implanted in the gate electrode of a transistor and are separately implanted into the source/drain region of the transistor. However, such method has two major disadvantages.
First, processing the polycrystalline silicon film 7 to form the gate electrodes 10 and 12 is difficult. As described above in conjunction with FIG. 7(c), the polycrystalline silicon film 7 contains three distinct regions: (1) a region in which no impurities are implanted, (2) the N.sup.+ type region 10, and (3) the P.sup.+ type region 12. Also, each of the three regions are simultaneously etched during the method to form the gate electrodes 10 and 12. However, the etching rates of the regions into which impurities are implanted are substantially faster than the etching rate of the regions in which no impurities are implanted. Therefore, after the etching of the region with no impurities is completed, the P.sup.+ type and N.sup.+ type regions 10 and 12 are over-etched, and thus, the characteristics and reliability of the transistor is severely and adversely affected. Also, the separation characteristics of the transistor is adversely affected. For example, when the P.sup.+ type and N.sup.+ regions 10 and 12 are over-etched, the gate electrodes 10 and 12 become thinner, the performance of the transistors is lowered due to the deteriorated shape of the electrodes 10 and 12, the gate oxide film 6 is damaged, and the reliability of various features of the transistor (e.g. the hot carrier resistance of the transistor) is lowered. Such problems are particularly obvious in the NMOS transistor which receives the phosphorous and arsenic ions P.sup.+ and As.sup.+ because the etching rate of polycrystalline silicon containing phosphorous is much higher than the etching rate of a polycrystalline silicon containing no ions.
The second problem with the method described above is that the time required to manufacture the transistors is substantially increased. Specifically, in order to add N type impurities and P type impurities to predetermined positions of the polycrystalline silicon film 7, to two masking steps must be added to the manufacturing steps shown in FIG. 5. (See FIGS. 7(a) and 7(b)). As a result, the cost to manufacture the transistors is increased.